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[资料] single cycle MIPS CPU with Verilog

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发表于 2016-7-25 16:32:27 | 显示全部楼层 |阅读模式

This project aims to implement a single cycle MIPS CPU with Verilog. For the beginning, the supported instructions would be:

add,
sub,
and,
or, slt
addi
, andi, ori
lw
, sw
beq

Hardware Specs:



  • Register File:32 × 32-bit Registers
  • Instruction Memory:1KB (256 × 32-bit )
  • Data Memory:32 Bytes (Memories are modeled in Verilog simply as an array of registers, so we did not care about the memory latency delay)
  • Address space: Text segment and data segment both begin at address 0x0000 for convenience, different from the real MIPS machine


code



single-cycle-mips-cpu-with-testbench.rar

7.29 KB, 下载次数: 5, 下载积分: IC币 -3 元

发表于 2017-9-26 00:20:51 | 显示全部楼层
好文,谢谢楼主。
发表于 2017-9-26 12:11:11 | 显示全部楼层
Very Elementry .
发表于 2018-3-14 21:54:44 | 显示全部楼层
一个漂亮的代码,谢谢你的分享
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