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[内部推荐] 招聘IC HW/FW 工程师, 方向 人工智能, 机器学习

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发表于 2018-6-2 09:41:11 | 显示全部楼层 |阅读模式
AI公司,上海 RD center 招聘 IC HW/FW 工程师,有意者, 请联系 leon.he@iluvatar.ai,  18621073029

ASIC Design Engineer

Job Description
Responsibilities:
1. Develop micro-architecture, write micro-architecture spec and other documents
2. Write RTL code, meet the function target and have good performance/power/area efficiency
3. Apply low power, DFT, DFD and other digital design techniques
4. Work with DV team to improve test plan and debug failed tests
5. Clean Lint, timing and other issues
6. May write firmware for embedded micro-controllers
7. Participate in silicon debugging

Qualifications:
1. Master in electrics or computer engineering.
2. At least 3 years working experience in ASIC logic design
3. Expert of Verilog RTL design
4. Experience of large digital ASIC project
5. Familiar with front-end EDA tools and flows
6. Programming skill in System Verilog, C/C++, perl, Tcl/tk, Python, etc. is preferred
7. Familiar with Linux Environment
8. Good communication in both Chinese and English
9. Good team player and strong sense of responsibility
10. Strong problem-solving skills
11. Have one or some of the following design experience: CPU, GPU, DSP, cache, ALU, memory controller.  














SOC Firmware engineer

Job Description
Responsibilities:
1. Be responsible for firmware development of system control unit. Focus on bootup related firmware and ARM based driver firmware development.
2. Design, implement and integrate the firmware modules from system architecture and functional specification.
3. Optimize the firmware performance for limited resource usage, low power consumption.
4. Support silicon bring-up, troubleshoot both hardware and software issues.
5. Write application/technical documents.

Qualifications:
1. Master with 5+ years or Bachelor with 8+ years of industrial experience in firmware development.
2. Proficient in C/C++, assemble programming is a plus
3. Knowledge of SPI, I2C, AMBA, JTAG, PCIE;
4. Minimum 3 years' experience in embedded software development with MCU architectures (e.g. 8051, ARM).
5. Experience in Video BIOS development is a plus.
6. Self-motivated, proactive, team work and achievement oriented.
7. Good communication skill and work well with cross-functional teams and technical leadership are big plus.





















SOC Design Engineer

Job Description
Responsibilities:
1. Be responsible for RTL code development of system control unit. Focus on one or multiple areas including: chip clk, reset, power control, fuse, thermal control, SOC IOs (GPIO, SPI, I2C, etc), etc.
2. Work with architect team (SOC/IP) to define block feature.
3. Work with SOC DV team to define the test plan.
4. Work with implementation team to close the timing.
5. Integrate block design into SOC.
6. Support silicon bring-up.

Qualifications:
1.Master with 5+ years or Bachelor with 8+ years of industrial experience in ASIC design.
2. Experience with Verilog HDL programming, Shell, Perl, Tcl are plus.
3. Be Familiar with verification.
4. Strong problem-solving skills.
5. Self-motivated, proactive, team work and achievement oriented.
6. Good communication skill and work well with cross-functional teams and technical leadership are big plus.























Frontend Integration Engineer

Job Description
Responsibilities:
1. Responsible for Front-End chip integration and implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
2. Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology.

Qualifications:
1. Familiar with Verilog RTL design and has experience of large digital ASIC project.
2. Familiar with Front-End flows (Synthesis/Timing/LEC/CDC/DFP/ECO etc.) and EDA tools (DesignCompiler/Genus, PrimeTime, Formality/Conformal, Spyglass/0in, VSI, ICC2/Innovus etc.)
3. Familiar with unix/linux and scripts (tcl, perl or python etc.)
4. Experience in Back-End flow is a plus
5. Experience in high-performance computing design/interfacing IP is a plus
6. Fluent English on talking, presentation and writing documents.
7. Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
8. Master with at least 3 years or Bachelor with at least 5 years working experience in ASIC area





















SoC Power Engineer

Job Description
SoC Power team is responsible for researching power expenditures and workload efficiency to identify architectural, micro-architectural strategies to improve power efficiency of the AI chips.

Responsibilities:
1. Be responsible to drive SoC level power simulation methodology and flow improvement.
2. Deliver regular power regression result to design team.
3. Set chip power targets and drive power goal convergence.
4. Closely working with design/architecture/system teams to debug the power bugs and improve the design power efficiency.
5. Develop the power flow to automate the power expenditures measurement.
6. Evaluate new low-power technologies and provide feedback to power ARCH team
7. Improve chip power efficiency of architectural level.
8. Support RTL designers using the power flow to do the power optimization work and improve their power efficiency on micro-arch level.

Qualifications:
1.6~7+ years’ experience for Master, or 9~10+ years’ experience for bachelor on low power related work
2. Good knowledge of Verilog/C-shell/TCL/Perl
3. Good knowledge of Lower Power design is a plus.
4. Experience in power verification is an asset



















DFT Engineer

Job Description
Responsibilities:
1. The candidate is expected to be responsible for following tasks:  
2. Participate in SOC full Chip DFT feature and architecture definition
3. Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic
4. Generate DFT related timing constraints and work for timing closure
5. Develop and verify high coverage and cost-effective test patterns for the production test
6. Evaluate and establish the advanced DFT tools and flow

Qualifications:
1. 8+ years’s experience for Bachelor or 5+ years for Master in DFT design and verification, test pattern development
2. Good Knowledge of Scan/ATPG, MBIST and boundary scan and other DFT techniques  
3. Good Knowledge of industry DFT tools like DFTMax, TetraMax ,TestKompress, FastScan, Tessent Mbist, SMS etc
4. Good knowledge of digital SoC/ASIC design, including STA, verification and RTL coding
5. Proficient in hardware description languages such as Verilog, System Verilog and VHDL
6. Good Knowledge of script language, such as Tcl, Python, Perl  
7. Good English communication skills
8. Strong commitment to schedule and work quality, good team player





















SoC PD Engineer

Job Description
Responsibilities:
Work with Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron chips for chip level design. The individual is expected to be an expert in multiple aspects in PD areas. The individual is also expected to be accountable for project delivery.

Qualifications:
1. MSEE with 3+ years or Bachelor with 5+ years of industrial experience in ASIC design
2. Experience in physical design of deep submicron digital ASIC chips
3. Hands on experience in large scale ASIC chip physical design
4. Knowledge in FinFET technology
5. Successfully gone through several complete product development cycles
6. Good listening, writing and speaking English
7. Good communication skills, strong interpersonal skills and the flexibility
8. Dedicated, hardworking and good team player
9. Power user of EDA tools from Synopsys (ICC/DC/PT/STAR-RC/RedHawk)
10. Familiar with Front-End EDA tools is a plus
11. Familiar with Unix/Linux environment and good at scripts























Deep Learning Verification Engineer

Job Description
Responsibilities:
1. Understand and closely discuss with architects / designers for hardware arch and micro-arch
2. Make up Block / IP / SOC level verification plan (methodology / testbench / testplan / coverage / ...) and improve cross environment reuse
3. Develop and debug testbench, tests and drive verification closure with coverage and other sign-offs
4. Develop and verify reference C-model for functional and performance purpose
5. Develop flows / tools to improve work efficiency
6. Communicate with software team for SW-HW interaction and code sharing

Qualifications
1.Computer Science, Electrical Engineering, Micro-Electronics related majors are preferred
2. 2+ years verification work experience (Bachelor/Master/PHD)
3. Good at Verilog/SystemVerilog/UVM/C/C++/Python
4. Good background in computer architecture is a plus
5. Familiarity with machine learning and deep learning is a plus
6. Familiarity with GPU computing (CUDA, OpenCL, cuDNN, TensorRT) is a plus
7. Good problem-solving ability is desired
8. Good communication skill is desired
9. Good team working is desired



















Deep Learning SW Architect

Job Description
Responsibilities:
1. Collaborate with HW team and system architectures to develop innovative Machine Learning Chip to extend the state of the art in deep learning performance and efficiency
2. Analyze and prototype key deep learning and data analytics algorithms and applications
3. Understand and analyze the interplay of hardware and software architectures on future algorithms and applications
4. Propose the direction of SW stack for machine learning, collaborating with architect, design and product teams

Qualifications
1. PhD in Computer Science, Electrical Engineering, ECE or Math with 8+ years of relevant work experience; or MS and 10+ years of relevant work experience in either application or driver; 3+ years of experience in Machine Learning specific area
2. Track record of crafting architectures to accelerate computational demanding algorithms and applications
3. Strong mathematical foundation in machine learning and deep learning
4. Strong background in deep-learning frameworks like Caffe, TensorFlow and Torch and familiar with backend implementation and optimization
5. Familiarity with Tensor XLA, ONNX, NNVM/TVM or LLVM is a plus
6. Familiarity with GPU computing (CUDA, OpenCL, cuDNN, TensorRT)
7. Good background in computer architecture
8. Experience with systems-level performance modeling, profiling, and analysis
9. Experience in characterizing and modeling system-level performance and executing comparison studies

















Senior Linux Kernel Driver Developer

What You'll Do
We are looking for a Linux Kernel Driver Developer with extensive experience in a Linux environment. The position involves the development and implementation of a kernel-mode driver for AI chips.

Who You'll Work With
You will work closely with hardware design team, compiler team and application team to understand the whole stack from software to hardware for advanced high-performance AI chips.

Job Description
Responsibilities:
1. Work closely with hardware and compiler team to identify the requirements for kernel-mode driver
2. Specify kernel-mode driver specification and architecture
3. Implement the kernel-mode driver development for high-performance AI chips
4. Implement and drive the feature development on different platform

Qualifications:
1. More than 5-year of experience in develop Linux kernel model driver
2. Experience in drivers for high-performance hardware is a plus;
3. Deep understanding to operation system and Linux kernel;
4. Knowledge of OpenCL or Cuda is optional;
5. Expert in C/C++ programming;
6. Good team collaboration and communication skills
7. Open-minded and passionate in learning new skills
8. Master/Bachelor in CS or related major.















Driver Engineer for High-performance Deep-learning Chips

What You'll Do
The software team is responsible for developing the whole software stack for our deep-learning chips. Responsibilities span from drivers and compiler development to implementing APIs such as OpenCL.
The team is seeking a dedicate driver engineer who is passionate about the advanced DL products and have a strong track record of building high performance and production quality software.

Job Description
Responsibilities:
1. Work closely with hardware to implement features for AI chips in different platform
2. New hardware bring-up and productization
3. Performance analysis and optimization


Qualifications:
1. Excellent programming skills and knowledge of C/C++.
2. Development experience on Unix or Linux.
3. User mode or kernel mode device driver development experience
4. Excellent software design, problem solving and debugging skills
5. Experience with OpenCL or Cuda APIs
6. Experience with driver or operating system development
7. Experience with software performance analysis and optimization
8. Strong communication and teamwork skills
9. Knowledge of Tensorflow, Caffe, LLVM or other DL/compiler framework is a plus
10. Knowledge of GPU/CPU architecture is a plus
11. Experience with parallel and asynchronous processing is a plus
12. BS/MS degree in Computer science or related major














Software Testing Leader


Job Description
Responsibilities:
In this position, your responsibility will be include but not be limited to:
1. Responsible for testing software stack from driver to application API interface for Deep Learning(DL) Asic in pre-silicon and post-silicon
2. Develop comprehensive test plans assuring the overall quality of ongoing projects
3. Lead testing and development team to drive quality through design and implementation
4. Lead and develop automation test framework suitable for testing DL software stack
5. Analyze and optimize performance based on current DL software and hardware

Qualifications:
1. More than 8-year of experience in software testing area including software development process, manual and automation testing,
2. Excellent in automation scripting language such as python, perl, ruby etc.
3. Familiar with linux driver/compiler testing
4. Good experience in whitebox testing
5. Excellent software performance testing, problem solving and debugging skills
6. Familiar with C/C++ programming
7. Familiar with Tensorflow, Caffe, LLVM, or other DL/compiler framework is a highly desired
8. Familiar with different DL models is a plus
9. Familiar with OpenCL or Cuda is a plus
10. Familiar with GPU/CPU architecture is a plus
11. Strong communication and teamwork skills
12. BS/MS degree in Computer science or related major
















SW SDK/Tool Developer

What You'll Do
We are looking for a SW SDK/tool engineer with good knowledge of the famous framework and network. The position involves the development and profiling of applications used on AI chips.

Who You'll Work With
You will work closely with hardware design team, driver team and application team to understand the whole stack from software to hardware for advanced high-performance AI chips.


Job Description
Responsibilities:
1. Analyze the function and performance of various machine learning/DL algorithms on existing/new architectures
2. Write special demo on popular framework like Tensorflow or Caffe2
3. Work with SW team to provide profiling tools

Qualifications:
1. 1-2 year work experience in DL application programming
2. Familiar with at least 1-2 frameworks like Tensorflow, Caffe2, PyTorch, …
3. Familiar with the popular network for DL
4. Good programming skills in python or C++
5. Good communication skills in both Chinese and English
6. BS or MS of computer science or other related major


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