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[猎头岗位] 高薪soc总线--办公上海、苏州、杭州、成都、

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发表于 2018-10-11 16:12:07 | 显示全部楼层 |阅读模式
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soc总线
JOB DESCRIPTION:
1. Module-level architecture definition and design;
2. Module-level RTL implementation;
3. Simulation/Verification at both module level and system level;
4. Module-level synthesis and timing analysis;
5. Writing design spec and report;
6. FPGA/silicon debug on related modules.
JOB QUALIFICATIONS:
1. Bachelor degree or Master degree in ASIC Design Relevant;
2. 3 years of SoC design experience;
3. Experience on AXI/AHB bus structure and arbiter.
4. Solid knowledge on digital IC design; Strong skills of Verilog RTL coding and simulation; Hands-on experiences on EDA tools, such as Cadence and Synopsys tools; Familiar with C language;
5. Relevant experiences on STB product;
6. Good communication skills and Good oral/written English.

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