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[资料] An Adaptive PLL Tuning System Architecture

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发表于 2019-11-30 18:13:01 | 显示全部楼层 |阅读模式
An adaptive phase-locked loop (PLL) architecture for high-performance tuning systems is described. The architec-
ture combines contradictory requirements posed by different performance aspects. Adaptation of loop parameters occurs contin-
uously, without switching of loop filter components, and without interaction from outside of the tuning system. The relationship of
performance aspects (settling time, phase noise, and spurious signals) to design variables (loop bandwidth, phase margin, and loop
filter attenuation at the reference frequency) are presented, and the basic tradeoffs of the new concept are discussed. A circuit im-
plementation of the adaptive PLL, optimized for use in a multiband (global) car-radio tuner IC, is described in detail. The real-
ized tuning system achieved state-of-the-art settling time and spectral purity performance in its class (integer- PLL's): a signal-to-
noise ratio of 65 dB, a 100-kHz spurious reference breakthrough signal under 81 dBc, and a residual settling error of 3 kHz after
1 ms, for a 20-MHz frequency step. It simultaneously fulfills the speedrequirementsforinaudiblefrequencyhoppingandtheheavy
signal-to-noise ratio specification of 64 dB.

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An Adaptive PLL Tuning System Architecture

发表于 2019-11-30 18:56:19 | 显示全部楼层
发表于 2019-12-2 09:12:53 | 显示全部楼层
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