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[SYNOPSYS 視訊教程][IC Compiler GUI Demo - Hierarchical Design Planning ]

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发表于 2014-7-17 13:37:43 | 显示全部楼层 |阅读模式
This training is delivered in Macromedia Flash format.  Information on system requirements, downloads and other installation issues, is available at FAQ.

Introduction 2:26
Introduction to the hierarchical design planning demo flow

Virtual Flat Placement 4:08
Analyze flat placement with color by hierarchy feature

Create & shape plangroup 4:20
Analyze created/shaped plangroup with flyline and net connectivity analyses

Clock Planning 3:52
Use clock browser and color layout by clock tree for clock planning

Pin Assignment 1:52
Use Feedthrough analysis GUI to preview feedthrough nets prior to pin assignment

Timing Budgeting 4:23
Use Timing Environment Check GUI to analyze unbudgetable pins, bottleneck cells and virtual IPO

Commit Hierarchy 1:30
Use flyline analysis to analyze committed soft macro pin locations

IC Compiler GUI Demo - Hierarchical Design Planning.part1.rar

13.9 MB, 下载次数: 70, 下载积分: IC币 -3 元

IC Compiler GUI Demo - Hierarchical Design Planning.part2.rar

9.46 MB, 下载次数: 46, 下载积分: IC币 -3 元

发表于 2015-12-11 13:38:28 | 显示全部楼层
111111111111111111111
发表于 2017-5-30 15:20:18 | 显示全部楼层
thanks for sharing
发表于 2019-10-2 09:00:37 | 显示全部楼层




编辑的编辑的编辑的
发表于 2019-10-2 09:01:06 | 显示全部楼层



编辑的编辑的编辑的
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